Phase locked loops are widely used in a variety of modern day electronic circuits including communication devices, integrated chips, etc. In general, phase locked loops are feedback systems configured to generate a signal having a fixed phase in relation to a reference signal.
More particularly, a phase locked loop (PLL) is a control circuit comprising a feedback loop having a phase detector that receives a reference signal and a feedback signal from a controlled oscillator. The phase of the input signals (e.g., reference signal, feedback signal) is defined by a point in time when relevant events (e.g., rising edges) occur. The phase detector determines a phase difference between the input signals (e.g., a time between rising edges) and based upon the measured phase difference generates an error signal that is output to a filter (e.g., a loop filter). The filter may be used to convert the error signal to an oscillator control signal that is used to control the frequency of the controlled oscillator.
Based on the oscillator control signal, the controlled oscillator oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback signal. In particular, the phase detector error signal is used to align the phase of the reference signal and the feedback signal. When the phases (e.g., clock edges) of the feedback signal and the reference signal are brought into alignment, the PLL is considered locked. Therefore, by measuring a phase difference that may be used to change a control signal provided to a controlled oscillator, a PLL is enabled to maintain a stable output signal having a constant phase angle relative to a reference signal.